Reliable Routing & Deadlock free massive NoC Design with Fault Tolerance based on combinatorial application.
Deepthi chamkur .V1, Vijayakumar.T2
1Deepthi chamkur V, Dept.., of Electronics & communication Engineering, SJBIT ,Visveshwarirh Technological University, Bangalore, India,.
2Mr. Vijayakumar .T, Asso., professor, Dept.., of Electronics & communication Engineering, SJBIT ,Visveshwarirh Technological University, Bangalore, India.
Manuscript received on May 30, 2012. | Revised Manuscript received on June 12, 2012. | Manuscript published on June 30, 2012. | PP: 425-433 | Volume-1, Issue-5, June 2012. | Retrieval Number: E0429051512/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Technological evolution enables the integration of billions of transistors on a chip. As VLSI technology scales, and processing power continues to improve, inter-processor communication becomes a performance bottleneck. On-chip networks have been widely proposed as the interconnect fabric for high performance SoCs. Recently, NoC architectures are emerging as the candidate for highly scalable, reliable, and modular on-chip communication infrastructure platform. This paper proposes the generalized binary de Bruijn (GBDB) graph based on combinatorial application as a reliable and efficient network topology for a large NoC. We propose a deadlock free & reliable routing algorithm to detour a faulty channel between two adjacent switches. In this implementation, using just two-layer VLSI layout, we can implement a NoC with any desired number of nodes. Note that current VLSI technology allows more than two wiring layers and the number is expected to rise in the future. Our experimental results show that the latency and energy consumption of the generalized de Bruijn graph are much less than those of Mesh and Torus. The low energy consumption of a de Bruijn graph-based NoC makes it suitable for portable devices which have to operate on limited batteries. Also, the gate level implementation of the proposed reliable routing shows small area, power, and timing overheads due to the proposed reliable routing algorithm.
Keywords: Network on chip (NoC), combinatorial application, energy consumption.