SOC Implementation of Soft-Error Tolerance in Asynchronous Burst Mode Circuits
Chandu Kumari1, T. Ravi Sekhar2
1Chandu Kumari, pursuing MTECH, VLSI, ECE Department, Sree vidyanikethan Engineering college, Tirupathi, India.
2T. Ravi Sekhar, Assistant professor, ECE Department, Sree vidyanikethan Engineering college, Tirupathi, India.
Manuscript received on May 27, 2012. | Revised Manuscript received on June 12, 2012. | Manuscript published on June 30, 2012. | PP: 265-268 | Volume-1 Issue-5, June 2012. | Retrieval Number: E0507061512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The problem of soft errors in asynchronous burst-mode machines (ABMMs), and we propose the solution is an error tolerance approach, which leverages the inherent functionality of Muller C- elements, along with a variant of duplication, to suppress all transient errors. The proposed method is more robust and less expensive than the typical triple modular redundancy error tolerance method and often even less expensive than previously proposed concurrent error detection methods, which only provide detection but no correction The solution is an error tolerance approach, which leverages the inherent functionality of Muller C-elements, along with a variant of duplication, to suppress all transient errors, which leverages a newly devised soft- error susceptibility assessment method for ABMMs, along with partial duplication, to suppress a carefully chosen subset of transient errors. Progressively more powerful options for partial duplication select among individual gates, complete state/output logic cones or partial state/output logic cones and enable efficient exploration of the tradeoff between the achieved soft- error susceptibility reduction and the incurred area overhead. Furthermore, a gate-decomposition method is developed to leverage the additional soft-error susceptibility reduction opportunities arising during conversion of a two-level ABMM implementation into a multilevel one. Extensive experimental results on benchmark ABMMs assess the effectiveness of the proposed methods reducing soft-error susceptibility, and their impact on area, performance, and offline testability.
Keywords: Asynchronous burst-mode circuits, soft errors, soft-error mitigation, soft-error susceptibility, soft-error tolerance.