Design of Low Power Double Data Rate 3 Memory Controller with AXI compliant.
Vijay kumar1, R K Karunavathi2, Vijay Prakash3
1Vijay kumar, M.Tech, VLSI DESIGN & ESD, Dept. of E & C, BIT, Bangalore.
2R K Karunavathi, Asstociate Professor, Dept. of E & C, BIT, Bangalore.
3Vijay Prakash, Asstociate Professor, Dept. of E & C, BIT, Bangalore.
Manuscript received on May 17, 2012. | Revised Manuscript received on June 25, 2012. | Manuscript published on June 30, 2012. | PP: 496-501 | Volume-1 Issue-5, June 2012. | Retrieval Number: E0547061512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. The next generation family of Double Data Rate (DDR)RAMs are DDR3 RAM. DDR3 RAMs offer numerous advantages compared to DDR2. These devices are lower power, they operate at higher speeds, offer higher performance (2x the bandwidth), and come in larger densities. DDR3 memory devices provide a 30% reduction in power consumption compared to DDR2, primarily due to smaller die sizes and the lower supply voltage (1.5V for DDR3 vs. 1.8V for DDR2). This paper represents the overall design and architecture of Low power Double Data rate 3(DDR3) memory controller. In this paper clock gating is used as a low power technique .
Keywords: The next generation family of Double Data Rate (DDR)RAMs are DDR3 RAM. DDR3 RAMs offer numerous advantages compared to DDR2.