Performance Comparison of Vedic Multiplier and Booth Multiplier
Anju
Ms. Anju, M. Tech Scholar, Electronics & Communication Engg, IMS Engineering College, Adhyatmik Nagar, Ghaziabad, (U.P), India.
Manuscript received on May 30, 2013. | Revised Manuscript received on June 11, 2013. | Manuscript published on June 30, 2013. | PP: 336-339 | Volume-2, Issue-5, June 2013. | Retrieval Number: E1846062513/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The performance of the any processor will depend upon its power and delay. The power and delay should be less in order to get a effective processor. In processors the most commonly used architecture is multiplier. If the power and delay of the multiplier is reduced then the effective processor can be generated. In this paper Vedic Multiplier and Booth Multiplier are implemented on FPGA and comparative analysis is done. The Comparison of these Architectures are carried out to know the best architecture for multiplication w. r. t. power and delay characteristics. The designs are implemented using VHDL in Modelsim 10.1 b and synthesis is done in Xilinx 8.2i ISE.
Keywords: Urdhva Tiryagbhyam, Vedic multiplier, Booth multiplier, Xilinx.