Performance Analysis of 6T, 8T and 10T SRAM Cell in 45nm Technology
M G Srinivasa1, Bhavana M S2
1M G Srinivasa, Department of Electronics and Communication Engineering, Maharaja Institute of Technology Thandavapura, Nanjangud Taluk, Mysore (Karnataka), India.
2Bhavana M S, Department of Electronics and Communication Engineering, Maharaja Institute of Technology Thandavapura, Nanjangud Taluk, Mysore (Karnataka), India.
Manuscript received on 12 April 2024 | Revised Manuscript received on 17 April 2024 | Manuscript Accepted on 15 June 2024 | Manuscript published on 30 June 2024 | PP: 12-16 | Volume-13 Issue-5, June 2024 | Retrieval Number: 100.1/ijeat.E444713050624 | DOI: 10.35940/ijeat.E4447.13050624
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The rise of portable battery-powered devices has emphasized the significance of low power IC design. Embedded SRAM units have become indispensable elements within contemporary SOCs due to their substantial footprint. In research circles, SRAM is highly regarded as a semiconductor memory type, highlighting its crucial role in the VLSI sector. In this paper, 6T, 8T and 10T SRAM cells design is estimated for power consumption and delay. This proposed work presents the schematic, simulation of analysis of 6T, 8T and 10T SRAM cells at 45 nm technology. The Cadence Virtuoso software is utilized for creating schematic diagrams and layouts, while the ASSURA library is employed for conducting design rule checks (DRC) and layout versus schematic (LVS) comparisons to verify the alignment between the layout and the schematic. In the process, a low VDD of 1 V is taken for the design. The results shows that 10T SRAM is efficient in terms of read and write delay and power consumptions.
Keywords: SRAM, Cadence. Tool, ASSURA, DRC, LVS
Scope of the Article: Electrical and Electronics