Design of High Speed 5:2 Compressor for Fast Arithmetic Circuits
N. Srinivas1, Y. Rajasree Rao2
1N. Srinivas, Department of Electrical Communication Engineering, Guru Nanak Institute of Technology, Hyderabad (Telangana), India.
2Y. Rajasree Rao, Department of Electrical Communication Engineering, St. Peters Engineering College, Hyderabad (Telangana), India.
Manuscript received on 13 June 2017 | Revised Manuscript received on 20 June 2017 | Manuscript Published on 30 June 2017 | PP: 329-333 | Volume-6 Issue-5, June 2017 | Retrieval Number: E5100066517/17©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multipliers are important components that dictate the overall arithmetic circuits’ performance. The most critical components of multipliers are compressors. In this paper, a new 5:2 compressor architecture based on changing some internal equations is proposed. In addition, using an efficient full-adder (FA) block is considered to have a high-speed compressor. The proposed architecture is compared with the best existing designs presented in the state-of the-art literature in terms of power, delay and area.
Keywords: Full-Adder (FA), XOR-XNOR, Multiplexers
Scope of the Article: Design and Application