Efficient Realization of a Novel Barrel Shifter in Cadence SoC Encounter
K. Murali Chandra Babu1, P. A. Harsha Vardhini2
1K.Murali Chandra Babu, Department of ECE, Vignan Institute of Technology and Science, Deshmukhi, Hyderabad (Telangana), India.
2Dr. P.A. Harsha Vardhini, Department of ECE, Vignan Institute of Technology and Science, Deshmukhi, Hyderabad (Telangana), India.
Manuscript received on 18 June 2019 | Revised Manuscript received on 25 June 2019 | Manuscript published on 30 June 2019 | PP: 460-464 | Volume-8 Issue-5, June 2019 | Retrieval Number: 6968068519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Reversible logic has the current development for the reason it consumes low power, which is the minimum requirement in the design of VLSI. A barrel shifter is the one which shift, rotate the data it is designed by using reversible gates. A novel Barrel shifter was designed in which it occupies less area with less delay. The proposed reversible barrel shifter was designed in VERILOG HDL and is simulated in XILINX ISE 12.4 simulator and chip level design was implemented in SoC encounter.
Keywords: Barrel Shifter, SoC, Reversible Gate, Garbage Ouputs.
Scope of the Article: Fuzzy Logics