Design & Implementation of Wallace Tree Multiplier and Kogge Stone Adder
Nikita Gulliya1, Anjali Baliyan2, Geetanjali Raj3
1Nikita Gulliya, Agnisys Technology, RnD Engineer, India.
2Anjali Baliyan, Department of Electronics and Communication, Maharaja Surajmal Institute of Technology, Delhi, India.
3Geetanjali Raj, Department of Electronics and Communication Engineering, ABES Engineering College, Ghaziabad (U.P), India.
Manuscript received on 18 June 2019 | Revised Manuscript received on 25 June 2019 | Manuscript published on 30 June 2019 | PP: 1392-1394 | Volume-8 Issue-5, June 2019 | Retrieval Number: E7381068519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: An increment in demand of portable devices makes low power device design and becomes an important field of research. Delay is one of the main design objective in integrated circuits after power. Three parameters which are power, area, and delay are always trade off. However speed and area are usually conflicting constraints, so that speed improvement results mostly in larger area. The multiplication and addition of two binary numbers are the most frequently and fundamental used arithmetic operations in microprocessors, data-processing application specific integrated circuits and digital processors. This research work will focuses on analyzing the delay of a Wallace tree multiplier and a Kogge Stone Adder by optimizing their circuits to increase the speed of the different digital circuits which are used in computations. Multipliers and adders are most important part in the digital processing or other applications. Therefore, multipliers and adders should be designed in such a way that their speed would be high and delay would be low. There are many attempts have been made to reduce the partial products which are generated in the multiplications and by using booth algorithm, whereas Wallace tree carry save adder structure have been used to sum the partial products to reduce time. In the full paper, the full implementation and simulation results will be discussed. Greatresults have beenachieved and comparison study has also been done with previous research work
Keywords: Wallace Tree Multiplier, Kogge Stone Adder,
Scope of the Article: Low-power Design