Accelerated PVT Analysis of UCM Architecture using Cadence ADE-XL
Rajkumar Sarma1, Cherry Bhargava2, Shruti Jain3
1Rajkumar Sarma, Department of Electronics & Electrical Engineering, Lovely Professional University, Phagwara (Punjab), India.
2Cherry Bhargava, Department of Electronics & Electrical Engineering, Lovely Professional University, Phagwara (Punjab), India.
3Shruti Jain, Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Waknaghat (Himachal Pradesh), India.
Manuscript received on 18 June 2019 | Revised Manuscript received on 25 June 2019 | Manuscript published on 30 June 2019 | PP: 1913-1919 | Volume-8 Issue-5, June 2019 | Retrieval Number: E7900068519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A Process-Voltage-Temperature (PVT) Variation check is run on the novel Universal Compressor based Multiplier (UCM) architecture, which promises for fast multiplication in ultra-low supply voltages (less than 0.9 V) for higher order operation. The analysis further shows that for 5×5 bit & 9×9 bit operation with supply voltage as low as 0.6 V, the delay has reduced by 0.73% & 5.05% (mean values) respectively than Wallace tree multiplier architecture. The analysis is carried out in Cadence Spectre tool using ADE-XL at CMOS 90 nm technology.
Keywords: Multiplier, Compressor Design, ADE-XL, Low Power, High Speed, Cadence Virtuoso, PVT Analysis, Delay Optimization.
Scope of the Article: Discrete Optimization