Assessment on the Adequacy of Current Supply Testing Methods in CMOS Operational Amplifier 
J. Sunil Kumar1, A. Deepthi2, U. Kaveri3, N. Ravalika Sharma4
1Mr. J. Sunil Kumar*, Assistant Professor, Vignan Institute of Management and Technology for Woman, Ghatkesar, Hyderabad, India.
2Ms. A. Deepthi, Vignan Institute of Management and Technology for Woman, Ghatkesar, Hyderabad, India.
3Ms. U. Kaveri, Vignan Institute of Management and Technology for Woman, Ghatkesar, Hyderabad, India.
4Ms. N. Ravalika, Vignan Institute of Management and Technology for Woman, Ghatkesar, Hyderabad, India.
Manuscript received on April 11, 2020. | Revised Manuscript received on May 15, 2020. | Manuscript published on June 30, 2020. | PP: 296-299 | Volume-9 Issue-5, June 2020. | Retrieval Number: 10.35940/ijeat.E9313.069520 | DOI: A1432109119/2020©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: As the CMOS innovation is downsizing, spillage power has gotten one of the most basic structure worries for the chip fashioner. This paper proposes examination on the adequacy of current gracefully testing strategies in cmos operational amplifiers. In this work, a two phase operational amplifier is structured and faults are infused utilizing 250nm innovation. We will assess the viability of current checking systems in distinguishing Bridge and open deformities in CMOS operational amplifiers. We ought to assess the identification capacities by utilizing two current testing strategies. The principal strategy comprises the oversight of the transient flexible current (IDDT) and the subsequent procedure comprises the observing of quiet gracefully current (IDDQ).The most probable resistive and open defects are infused utilizing fault infusion extra transistors. Exhibitions of the CMOS operational amplifier are additionally assessed after each issue infusion. Spice stimulation ought to be done to compare about the proposed test systems and assess the best performing one. We ought to assess the recognition abilities by utilizing two current testing procedures. The primary system comprises the oversight of the transient gracefully current (IDDT) and the subsequent method comprises the checking of quiet flexibly current (IDDQ). The most probable resistive and open deformities are infused utilizing fault infusion extra transistors. Exhibitions of the CMOS operational amplifier are likewise assessed after each fault infusion. Flavor re-enactments ought to be done to look at the proposed test strategies and assess the best performing one.
Keywords: Current testing; Fault infusion, operational amplifier.