A Survey on The Performance Analysis of FinFET SRAM Cells for Different Technologies
Girish H1, Shashi Kumar D. R2
1Girish H, Research Scholar, Visvesvaraya Technological University RRC, Machhe, Belagavi (Karnataka), India.
2Dr. Shashi Kumar D. R, Professor and Head of Department, Department of Computer Science Engineering, Cambridge Institute of Technology, Bangalore (Karnataka), India.
Manuscript received on 15 August 2015 | Revised Manuscript received on 25 August 2015 | Manuscript Published on 30 August 2015 | PP: 133-136 | Volume-4 Issue-6, August 2015 | Retrieval Number: F4193084615/15©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a survey on the performance analysis of FinFET SRAM Cells for different technologies. Industry requires high performance low power devices and memories. CMOS devices scaled down to reduce the size. As CMOS devices are scaled down the variation in the design metrics like SNM, Leakage power and delay increases. FinFET is an emerging technology in the VLSI design to overcome the drawbacks of CMOS. FinFET has become the most promising alternatives to conventional CMOS. In this paper, comparison of conventional CMOS, Independent-Gate (IG) and Tied Gate (TG) FinFET SRAM standard cells performance analysis is done with respect to leakage power, Static Noise Margin (SNM) and delay.
Keywords: FinFET, SRAM, SNM, Leakage Power, Delay.
Scope of the Article: Structural Reliability Analysis