FPGA Based 12-Tuple Fast Packet Classification IP Core for SoC Design
Adnan Hussein Ali1, Begared Salih Hassen2, Aassia Mohammed Ali Jassim3
1Dr Adnan Hussein Ali, Institute of Technology, Middle Technical University, Baghdad, Iraq.
2Begared Salih Hassen, Institute of Technology, Middle Technical University, Baghdad, Iraq.
3Aassia Mohammed Ali Jassim, Institute of Technology, Middle Technical University, Baghdad, Iraq.
Manuscript received on 15 August 2015 | Revised Manuscript received on 25 August 2015 | Manuscript Published on 30 August 2015 | PP: 243-246 | Volume-4 Issue-6, August 2015 | Retrieval Number: F4221084615/15©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Due to increased demand for the speed of communication over Internet. Packet header analysis and classification needs to be performed at same speed in network devices to provide Quality of Service (QoS). As network speed is increasing quickly, high speed packet classification is required at wire speed. In this paper, we propose a novel FPGA based pipelined architecture intended for 12-tuple packet classification on gigabit networks such as 1G/10G/40G/100G. Our solution also enables wire speed packet classification which can be used in Ethernet based SoC designs. It takes one clock cycle to classify the packet after arrival of required information. The proposed method has been designed and synthesized on FPGA using VHDL and can be reused in powerful high speed Ethernet based communication devices. The architecture is optimized for high speed processing and consumes only small amount of FPGA resources. More than 85% throughput can be achieved.
Keywords: IP, FPGA, Packet Classification. Router, SoC
Scope of the Article: Classification