Design and Performance Analysis of Hybrid Full Adder using Fin FET 40nm Technology
P. Sreekanth1, K. Sri Rama Krishna2, Sadulla Shaik3
1P. Sreekanth, electronics and communication engineering, VR Siddhartha engineering college, Vijayawada, India.
2K. Sri Rama Krishna, electronics and communication engineering, VR Siddhartha engineering college, Vijayawada, India.
3Sadulla Shaik, electronics and communication engineering, KKR & KSR institute of Technology and sciences, vinjanampadu, Guntur, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 4521-4525 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8053088619/2019©BEIESP | DOI: 10.35940/ijeat.F8053.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Designing a low power and energy efficient circuits in Fin FET technology is of great Challenge. This paper presents the internal logic structure and circuit operation using the devices, CMOS and Fin FETs for designing the hybrid adder cells. At transistor level, CMOS and Fin FET based hybrid full adder (HFA) and improved hybrid full adder (IHFA) is designed. Simulations are carried out using the cadence tool in UMC 40nm and the performance analysis of these HFA and IHFA are compared with the 40nm Fin FET technology. It is observed that IHFA is better when compared with the HFA in terms of propagation delay, power consumption and energy delay product. IHFA achieves the higher drive current and low leakage power for better mobility and transistor scaling as compared with HFA.
Keywords: Low-power, energy efficient, Fin FET, Internal logic structure, hybrid adder, ultralow voltage.