A Robust and Efficient Fault-Resilient Rad Hard ADPLL
Varsha Prasad1, S Sandya2
1Varsha Prasad*, Department of ECE, Nitte Meenakshi Institute of Technology, Bangalore, India.
2Dr S Sandya, Department of ECE, Nitte Meenakshi Institute of Technology, Bangalore, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 1116-1124 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8084088619/2019©BEIESP | DOI: 10.35940/ijeat.F8084.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Typically, classical PLLs adopt analog design methods. However integrating PLL with noise-prone application environment is highly tedious and somewhere confined. As per current knowledge majority of PLLs apply Analog Loop Filters (ALFs) and Voltage Controlled Oscillators which are practically highly complicated to integrate with noisy environment. Even the traditional PLLs can’t be ported to the advanced processors. In last few years, the emergence of deep-submicron CMOS technologies have enabled digitization of major traditional analog circuits, comprising the analog PLLs that as a result could be vital to overcome above mentioned issues and to achieve more efficient solution than classical analog implementation.
Keywords: ADPLL, Radhard, FDLC-ADPLL