VLSI based Error Correction Code Using Fault-tolerant Parallel FFTs 
Sakhamuri Sravanthi1, Rajendra Prasad Somineni2
1SakhamuriSravanthi, Research Scholar, Department of ECE, Shri JJT University, Jhunjhunu, Rajasthan, India. |
2Rajendra Prasad Somineni, Professor, Department of ECE,VNR Vignana Jyothi Institute of Engineering an Technology, Hyderabad, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 952-956 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8258088619/2019©BEIESP | DOI: 10.35940/ijeat.F8258.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The difficulty in the signal processing and communication systems increase year by year. This results in the on demand for scaling and integration with the help of advanced CMOS technologies. Soft errors are reliability thread on modern digital world which explains the need of protection against errors in digital circuit applications. In some applications, techniques like Algorithm based fault tolerance (ABFT) are used to detect and correct error with the help of algorithm properties. As the filters are the basic building blocks in most of systems, FFTs are used with the protection scheme using parseval checks which detects and corrects errors. The proposed technique consume low power. A technique is proposed using parseval checks to protect the circuits from single bit errors and is further improved for multi bit errors detection and correction and are evaluated in area and delay parameters.
Keywords: ECC, ABFT, softerrors, TMR, Parseval Checks.