Multiplication Technique in Residue Number System
Tukur Gupta1, Shamim Akhter2, Shaheen Khan3, Saurabh Chaturvedi4
1Tukur Gupta, Ph.D. Scholar, Department of Electronics and Communication Engineering (ECE), Jaypee Institute of Information Technology, Noida, India.
2Shamim Akhter, Assistant Professor, Department of ECE, Jaypee Institute of Information Technology, Noida, India.
3Shaheen Khan, Assistant Professor, Department of ECE, Mewat Engineering College (Waqf), Haryana, India.
4Saurabh Chaturvedi, Assistant Professor, Department of ECE, Jaypee Institute of Information Technology, Noida, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 1037-1041 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8288088619/2019©BEIESP | DOI: 10.35940/ijeat.F8288.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the modulo multiplication technique in residue number system (RNS) using Vedic mathematics. Residue number system supports fast mathematsical computation. In this paper, the use of the combination of RNS and Vedic mathematics has improved the computation time for modulo multiplication operation. The proposed modulo multiplier is implemented in VHDL and synthesized using Xilinx ISE 14.1.The performance comparison analysis in terms of area, power and delay is done between the proposed technique and direct computation. The performance of the multiplier circuit has been compared using the 32 nm standard cells available in Synopsys Design Compiler. The presented Vedic modulo multiplier is efficient in terms of speed for large input data sizes.
Keywords: HDL design, Vedic mathematics, residue number system (RNS), lookup table (LUT), modular multiplication.