High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder
Jaya Koshta1, Kavita Khare2
1Jaya Koshta*, Department of Electronics and Comm. Engg., MANIT, Bhopal, India.
2Kavita Khare, Department of Electronics and Comm. Engg., MANIT, Bhopal, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 1235-1238 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8380088619/2019©BEIESP | DOI: 10.35940/ijeat.F8380.088619
Open Access | Ethics and Policies | Cite | Mendeley
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures.
Keywords: HEVC, Video compression, Motion estimation (ME), Summation of absolute differences (SAD), FPGA.