High Performance of Wallace Tree Multiplier Stacking Circuit
M.Venkata Ramanaiah1, G. Anjaneyulu2, Sudhakar Alluri3
1M. Venkata Ramanaiah, Department of ECE, CMR Institute of Technology, JNTUH, Hyderabad, (T.S), India.
2G. Anjaneyulu, Department of ECE, CMR Institute of Technology, JNTUH, Hyderabad, (T.S), India.
3Sudhakar Alluri, Department of ECE, CMR Institute of Technology, JNTUH, Hyderabad, (T.S), India.
Manuscript received on September 12, 2019. | Revised Manuscript received on October 05, 2019. | Manuscript published on October 30, 2019. | PP: 1-5 | Volume-9 Issue-1, October 2019 | Retrieval Number: F8952088619/2019©BEIESP | DOI: 10.35940/ijeat.F8952.109119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper one novel double counter proposed which is quick when contrasted with another normal’s parallel counters. First, we are designing binary counter using solely full adders, and after with new symmetric stacking method. We are evaluating these two techniques and displaying how the symmetric stacking method is decreasing the x-or gate delays in the essential route of the binary counter. This kind of our proposed counter is very useful in the existing counter based totally Wallace tree multiplier design. With this new symmetry stacking counter we are lowering delay and increasing the performance of multipliers in VLSI circuits. We are designing and simulating our proposed quick binary counter using Xilinx ISE layout suite14.7.
Keywords: Counter, High speed, low power, Multiplier, Wallace tree, VLSI.