Modified Keeper Controlled Domino Circuit for Low Power High Performance Wide Fan in OR Gates
Manish Tiwari1, Vijayshri Chaurasia2, Bhavana P. Shrivastava3, Laxmi Kumre4
1Manish Tiwari*, Electronics and Communication Department, MANIT Bhopal, M.P., India.
2Vijayshri Chaurasia, Electronics and Communication Department, MANIT Bhopal, M.P., India.
3Bhavana P. Shrivastava, Electronics and Communication Department, MANIT Bhopal, M.P., India.
4Laxmi Kumre, Electronics and Communication Department, MANIT Bhopal, M.P., India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 3121-3126 | Volume-8 Issue-6, August 2019. | Retrieval Number: F9168088619/2019©BEIESP | DOI: 10.35940/ijeat.F9168.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A novel modified keeper technique has been proposed in this paper for domino logic circuits implemented as wide fan in OR gate. Few circuit parameters as capacitivie loading and delay are major concerns for OR gates in deeper technology nodes. This design focuses on a comparator block with modified dual keeper to maintain the output logic state. Additionally it comprises of a delay loop to limit the contention current. The proposed design reduces the input capacitive loading and total power consumption by the circuit, while keeping the speed of operation same. It was compared with latest domino circuit techniques and the proposed design MKCD has achieved a reduction of 41% in power consumption in 64 bit configuration as compared to conventional domino circuit SFLD. Average noise immunity has also increased by more than twice as compared to SFLD. The simulations were performed using 90nm PTM low power models.
Keywords: Dynamic logic circuits, OR gate domino, Modified keeper, Low power digital VLSI design.